The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device such as a dynamic random access memory (DRAM).
A sense amplifier (hereinafter referred to as the SA) region of a DRAM has the second largest area ratio next to a memory cell. Hence, reducing the layout area of the sense amplifier region is important for cost reduction. It is therefore necessary that a sense amplifier circuit element be compressed and disposed within a narrow cell pitch. Layout compression is generally achieved by providing the gate and source/drain diffusion layer of a transistor with a special layout form that is different from the layout form of a common logic circuit region.
For example, a semiconductor memory device proposed in Japanese Unexamined Patent Publication No. Hei 10 (1998)-303387 is capable of reducing the planar area of a region where a sense amplifier circuit is formed. Further, a variety of exemplary configurations of a common sense amplifier are proposed, for instance, in Japanese Unexamined Patent Publication No. 2005-322380.